Sr. ASIC/FPGA Design Verification Engineer (Compute Test Division; North Reading, MA) jobs in United States
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Teradyne ยท 6 hours ago

Sr. ASIC/FPGA Design Verification Engineer (Compute Test Division; North Reading, MA)

Teradyne is a global leader in test and automation solutions, dedicated to powering next-generation technologies. The company is seeking a Sr. ASIC/FPGA Design Verification Engineer to focus on FPGA verification, including reviewing design requirements, writing verification plans, and collaborating with various engineering teams.

Consumer ElectronicsIndustrialIndustrial Automation
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H1B Sponsor Likelynote

Responsibilities

Review of design requirements documents
Writing and reviewing verification plans
Testbench architecture and implementation
Reference model development
Test writing and debug
Functional/code coverage collection, merging and closure
Managing bugs/issues in a bug tracking tool
Collaboration with logic designers, board designers and software designers
Communicating status to project leadership

Qualification

Digital logic verificationSystemVerilogUniversal Verification Methodology (UVM)FPGA designTestbench architecturePythonLinux developmentProblem debuggingCommunicationTeam playerCollaboration

Required

BS/MS (or higher) in Electrical/Computer Engineering or similar technical field
Minimum of 10+ years of industry experience
Knowledgeable in digital logic verification, preferably using SystemVerilog & Universal Verification Methodology (UVM)
Familiarity with PCIe, Ethernet, AXI, DDRx, I2C, SPI
Familiarity with scripting language such as Python, TCL and Perl
Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities
Excellent written and oral communication skills
Familiarity with a digital simulation tool such as Synopsys, Cadence, or Mentor
Familiarity with bug/issue tracking tools like JIRA
Familiarity with C/C++
Familiarity in the use of a source control tools
Familiarity working in a Linux based development environment

Preferred

Experience with the Cadence Xcelium simulation tool
Experience with the digital logic verification using SystemVerilog & Universal Verification Methodology (UVM)
Experience in logic design writing RTL in Verilog HDL
Experience with physical design tools from FPGA vendors (Vivado and/or Quartus)
Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)
Experience with continuous integration/continuous development (CI/CD) development flows

Benefits

Medical
Dental
Vision
Flexible Spending Accounts
Retirement savings plans
Life and disability insurance
Paid vacation & holidays
Tuition assistance programs
And more.

Company

Teradyne

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Teradyne is a supplier of automatic test equipment used to test complex electronics used in consumer electronics.

H1B Sponsorship

Teradyne has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (28)
2024 (32)
2023 (23)
2022 (20)
2021 (27)
2020 (33)

Funding

Current Stage
Public Company
Total Funding
unknown
1978-01-13IPO

Leadership Team

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Greg Smith
President and CEO
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Michelle Turner
Chief Financial Officer
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Company data provided by crunchbase