Teledyne Judson Technologies ยท 1 month ago
Staff Logic Design Engineer
US - Milpitas, CA
Full-time
Onsite
Senior Level, Lead/Staff
$142K/yr - $189K/yr
7+ years expTeledyne Judson Technologies is a leader in advanced technology solutions for various industrial markets. They are seeking a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture, analysis, and emulation, working on FPGA-based systems and collaborating with cross-functional teams.
ElectronicsManufacturing
Responsibilities
Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management
Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency
Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization
Integrate PCIe IP cores, DMA engines, and custom protocol decoders
Build SystemVerilog/UVM testbenches for block and system-level verification
Conduct simulation, waveform analysis, and functional coverage to ensure robust design
Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms
Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap)
Create design specifications, interface documents, and verification plans
Participate in design/code reviews and contribute to continuous improvement of design practices
Qualification
Required
BS in EE, CS or Computer Engineering required
7+ years of experience in digital logic design for FPGA or ASIC
Strong proficiency in Verilog/SystemVerilog RTL design
Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA
Experience with Monitoring and/or Test & Measurement tools
Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts
Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure
Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator)
Solid understanding of CDC, clock domain design, and reset strategies
Preferred
Experience with protocol analyzers, packet capture, and timestamping logic
Familiarity with AXI interconnects, memory controllers, and high-speed buffering
Exposure to SERDES, PCIe IP integration, and link training/debug
Scripting experience (Python, Tcl) for automation and test infrastructure
Experience with hardware/software co-design, register maps, and embedded firmware interaction
Prior work in test & measurement or semiconductor validation environments
Company
Teledyne Judson Technologies
Teledyne Judson Technologies is a designer and manufacturer of high performance infrared detectors and accessory products
51-200 employees
Funding
Current Stage
Growth StageTotal Funding
unknown2008-02-04Acquired
2000-03-01Private Equity
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