Ayar Labs · 3 weeks ago
Principal Engineer, ASIC Physical Design
San Jose, CA
Full-time
Onsite
Lead/Staff
$180K/yr - $230K/yr
10+ years expAyar Labs is revolutionizing computing by moving data with light, aiming to enhance processing power for various applications. The ASIC Physical Design Engineer will be responsible for the physical design and integration of complex SoCs, focusing on synthesis, place and route, timing closure, and physical verification.
AI InfrastructureArtificial Intelligence (AI)ComputerHardwareInformation TechnologySemiconductor
Responsibilities
Physical design of blocks containing digital and custom analog / mixed-signal blocks
Contribute to design for test (DFT) methodologies
Contribute to automated design methodologies for ASIC physical design
Perform ASIC physical design (synthesis, place-and-route), static timing analysis (STA), and physical verification (DRC/LVS) of mixed-signal SoCs
Coordinate and drive activities across multiple designers
Contribute across a broad range of CAD methodologies to improve design implementation flows
Qualification
Required
BS or MS in Electrical Engineering, Computer Engineering, or related fields
10+ years of work experience in ASIC physical design
History of leading successful block implementations integrating custom IP in leading edge process nodes
Proficient in Verilog RTL
Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS) tools and flows
Mastery of timing constraints and deep understanding of static timing analysis
Proficient in clock tree synthesis methodologies and customization
Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc
Proficient in ASIC signoff methodologies, checklists, and requirements
Proficient in scripting or programming languages
Preferred
Working knowledge of the Cadence Virtuoso design environment for manual schematic entry and layout
Programming experience in Python
Experience with 3DIC implementation methodologies and custom tool flows
Knowledge of high-speed SerDes or SerDes components
Experience working in conjunction with external ASIC services providers
Performed silicon debug and triage of physical design-related issues
Company
Ayar Labs
Ayar Labs develops optical I/O solutions for large-scale AI workloads to accelerate data movement within AI systems.
51-200 employees
H1B Sponsorship
Ayar Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (14)
2024 (2)
2023 (7)
2022 (4)
2021 (4)
2020 (2)
Funding
Current Stage
Late StageTotal Funding
$374.65MKey Investors
Capital TENBoardman Bay Capital ManagementLockheed Martin Ventures
2024-12-11Series D· $155M
2023-05-24Series C· $25M
2022-04-26Series C· $130M
Leadership Team
Mark Wade
President and CEO, Co-Founder
Alex Wright-Gladstein
Co-Founder and Advisor
Recent News
2025-11-23
2025-11-19
Company data provided by crunchbase