Qualcomm · 1 day ago
CAD and PPA Methodology Engineer
San Diego, CA
Full-time
Onsite
Mid, Senior Level
$162K/yr - $243K/yr
4+ years expQualcomm Technologies, Inc. is seeking a CAD and PPA Methodology Engineer to join their Graphics team. The successful candidate will develop new flows and methodologies to enhance power, performance, and area on GPU cores while collaborating with design and implementation teams.
Telecom & CommunicationsArtificial Intelligence (AI)SoftwareGenerative AITelecommunicationsWireless
Responsibilities
Help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores
Collaborate with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores
Implementation and delivery of GPU cores from RTL to GDSII
Semi-custom design flow and methodology development
Identifying areas for flow and process improvements
Verilog and System-Verilog languages
RTL synthesis using physically aware tools
Design constraint management for power, timing, clocking, interfaces
Formal Verification for RTL-netlist and netlist-netlist checks
Clock Tree Analysis and Optimization
ECO methods for functional and timing fixes
Managing design goals and tradeoffs in power, performance, and area
Qualification
Required
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience
OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience
OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience
Basic understanding of RTL design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification
Collaboration with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores
Preferred
At-least 5-7 years of experience developing methodologies for PPA improvement
Basic understanding of digital design and RTL development
Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower, PrimeTime and Prime Closure
Script writing experience in UNIX shell, Python, Perl and/or TCL
Excellent interpersonal and analytical skills as well as ability to work independently
Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
Recent News
2026-02-12
San Diego Union-Tribune
2026-02-12
2026-02-12
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