Celestial AI · 7 hours ago
Senior Manager, ASIC Design
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
$205K/yr - $235K/yr
8+ years expCelestial AI is a company focused on advancing data center infrastructure through innovative interconnect technology. The Senior Manager, ASIC Design will lead the ASIC chip design team, overseeing the development of high-performance ASICs while ensuring technical excellence and timely project delivery.
Semiconductors
Responsibilities
Lead a team of high performing ASIC design engineers responsible for RTL design of IPs, subsystems and SOCs supporting Celestial AI’s photonic fabric roadmap
Develop project schedules, define milestones, allocate resources, manage budgets and ensure timely delivery of high-quality designs that meet product functional and performance goals
Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices
Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques
Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality
Mentor the team, foster a culture of continuous learning and actively help with career development
Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in timely fashion to support team deliverables
Qualification
Required
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Minimum of 8+ years of ASIC/SOC digital design experience and 3+ years of people management experience
Excellent leadership, communication, team building and stakeholder management skills
Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies
Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies
Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
Proficiency with front end development tools/methodologies, and scripting for automation and flow integration
Preferred
PhD in Electrical Engineering, Computer Engineering, or a related field
Experience managing relationships with external design partners, IP vendors, and foundries
Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test
Benefits
Health, vision, dental and life insurance
Collaborative and continuous learning work environment
Company
Celestial AI
AI is touching our lives and driving breakthroughs in healthcare, finance, autonomous systems, and countless other domains.
51-200 employees
H1B Sponsorship
Celestial AI has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (15)
2024 (10)
2023 (4)
2022 (7)
2021 (1)
Funding
Current Stage
Growth StageLeadership Team
David Lazovsky
Founder, CEO
Recent News
Venture Capital Access Online
2025-03-13
2025-03-13
Company data provided by crunchbase