Broadcom · 2 hours ago
IP Integration Engineer
Fort Collins, CO
Full-time
Onsite
Mid, Senior Level
$91K/yr - $146K/yr
5+ years expBroadcom is focused on enabling customers to develop products with a competitive advantage through best-in-class technology platforms. The IP Integration Engineer will be part of a cross-functional design team developing die-to-die and die-to-memory PHY IP for custom silicon ASIC products, ensuring integration and optimization of these components.
MobileSemiconductorWireless
Responsibilities
Develop a detailed understanding of Broadcom's die-to-die PHYs
Work with multiple cross functional teams--analog design, digital design, physical composition, DFT, timing, and customers--to build PHYs
Work with physical composition teams and interposer design teams
Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs
Work with teams to analyze power integrity (droop, EM, etc…) in various use cases and workloads
Develop/write PHY integration documentation for ASIC composition teams
Develop list of Checklist task for integration of PHY IP into ASICS
Work with IP build teams to complete quality crosschecks to ensure the quality of the PHYs
Help support customer and ASIC PHY integration questions
Qualification
Required
A Bachelor's Degree in Electrical or Computer Engineering or equivalent, and 5+ years of related experience; or Masters degree and 3+ years of related experience
Understanding of design trade offs for power, area, and speed in ASIC designs
Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC
Basic understanding of modern FET architecture including FinFET and Gate All-Around (GAA) topologies
Experience with Cadence Innovus or equivalent toolset
Experience in reading timing reports from static timing tools such as Tempus or Primetime
Strong verbal, written communication
Team player that can easily work with different personalities and skill levels
Ability to multitask and manage multiple technical issues in parallel
Well organized, methodical, and detail oriented
Must develop, accurately track, and meet commitments to product or engineering development schedules
Preferred
Experience with the Cadence Virtuoso design environment
Experience or coursework with RTL languages (i.e SystemVerilog, Verilog, VHDL)
Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc
Familiar with timing reports and strategies for fixing violations
Experience or familiarity with Ansys Redhawk
Working knowledge with AI tools such as Chat GPT, Gemini, and/or Cursor
Benefits
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Company
Broadcom
Broadcom is a designer, developer, and global supplier of a broad range of analog and digital semiconductor connectivity solutions.
10001+ employees
H1B Sponsorship
Broadcom has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (92)
2024 (77)
2023 (79)
2022 (112)
2021 (110)
2020 (89)
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-10-31Post Ipo Equity
2015-05-28Acquired
1998-04-17IPO
Leadership Team
Greg Singh
CTO for APJ, Enterprise Security Group
Kirsten Spears
CFO and CAO, Broadcom
Recent News
2026-01-01
IEEE Spectrum
2025-12-31
2025-12-30
Company data provided by crunchbase