Apply on Employer Site

Cadence · 1 week ago

Senior Principal DFT Design Engineer

San Jose, CA

Full-time

Onsite

Senior Level, Lead/Staff

5+ years exp

Cadence is a technology company that hires and develops leaders and innovators. They are seeking a Senior Principal DFT Design Engineer with expertise in Design for Test (DFT) and a strong background in SoC/ASIC Digital Design to enhance their technology impact.

AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)

Should possess intimate knowledge of DFT insertion flows

Basic scan chain insertion using synthesis or other software tools

Experience in compression scan insertion, LBIST and other scan technologies

Intimate knowledge of memory build-in self-test (MBIST)

Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals

Debug and Analysis of failures to improve fault coverage

Verification of ATPG testbenches and debugging root cause of simulation mis-compares

Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687

Knowledge of timing analysis and equivalency checks would be added bonus

Ability to work in collaborative team environment

Prior experience with Cadence tools and flows is highly desirable

Should be able to finish DFT tasks independently

Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems

Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers

Self-driven and committed individual who can work in a fast-paced project environment

Qualification

DFT Design experienceAutomatic Test Pattern GenerationMemory Built-In Self-TestScan chain insertionCompression scan technologiesJTAG 1149.1/6 knowledgeCollaborative team environmentFast-paced project environmentProblem-solving skills

Required

Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)

Should possess intimate knowledge of DFT insertion flows

Basic scan chain insertion using synthesis or other software tools

Experience in compression scan insertion, LBIST and other scan technologies

Intimate knowledge of memory build-in self-test (MBIST)

Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals

Debug and Analysis of failures to improve fault coverage

Verification of ATPG testbenches and debugging root cause of simulation mis-compares

Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687

Ability to work in collaborative team environment

Should be able to finish DFT tasks independently

Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems

Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers

Self-driven and committed individual who can work in a fast-paced project environment

Preferred

US citizenship preferred

Knowledge of timing analysis and equivalency checks would be added bonus

Prior experience with Cadence tools and flows is highly desirable

Hands-on knowledge of synthesis, verification and debugging Verilog testbenches

Company

Cadence

Glassdoor4.3

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.

Founded in 1988

San Jose, California, USA

10001+ employees