Cisco · 5 days ago
ASIC Engineering Technical Leader
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$169K/yr - $241K/yr
10+ years expCisco is a leading company in networking technology, delivering innovative solutions for various sectors. They are seeking an ASIC Engineering Technical Leader to manage the design and architecture of high-performance ASICs, focusing on Design-for-Test and collaborating with multiple teams throughout the implementation and validation phases.
Communications InfrastructureEnterprise SoftwareHardwareSoftware
Responsibilities
Manages the definition, architecture and design of high performance ASICs
Owns applications or multiple complex functional areas
Oversees reusable code and its applications
Creates re-usable code that promotes efficiencies in new ways
Debugs at system level
Consults for architecture and design decisions outside of depth areas
Provides robust design solutions across product
Re-enforces guidelines/standards across teams
Defines verification strategies
Coordinates with appropriate stakeholders to integrate into PD and DV flows
Owns infrastructure and testing environments
Leads and designs the building blocks of multiple channels
Applies and drives the design methodology from conception to production
Influences and collaborates with teams to ensure specifications and requirements are met
Leads technical expertise of a physical design function
Interfaces with vendors and design leads on full chip timing closure, PI, and PV
Owns the full electrical planning and specifications of electrical interfaces
Develops multiple solutions, first test vehicles and performs verification and validation
Qualification
Required
Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience
Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure
Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators
Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation
Scripting skills: Tcl, Python/Perl
Preferred
Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
DFT CAD development – Test Architecture, Methodology and Infrastructure
Benefits
Medical, dental and vision insurance
A 401(k) plan with a Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
Annual bonuses subject to Cisco’s policies
Company
Cisco
Cisco develops, manufactures, and sells networking hardware, telecommunications equipment, and other technology services and products. It is a sub-organization of Cisco Press.
10001+ employees
H1B Sponsorship
Cisco has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (1238)
2024 (1231)
2023 (1273)
2022 (2127)
2021 (1991)
2020 (1173)
Funding
Current Stage
Public CompanyTotal Funding
unknown1990-02-13IPO
Leadership Team
Chuck Robbins
Chair and CEO
Carl Solder
Chief Technology Officer - Cisco System Australia/New Zealand
Recent News
2026-01-08
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2026-01-07
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