Synopsys Inc · 2 days ago
Analog Models & Verification Engineer, Architect - 13485
Chandler, AZ
Full-time
Onsite
Senior Level
7+ years expSynopsys Inc is a leader in chip design and verification, driving innovations in the Era of Pervasive Intelligence. The Analog Models & Verification Engineer will focus on creating high-fidelity behavioral models for analog circuits, enhancing the performance and quality of connectivity products through rigorous verification and collaboration across engineering teams.
Electronic Design Automation (EDA)Information ServicesInformation TechnologySoftware
Responsibilities
Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data
Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator)
Ensure models accurately capture all relevant functionalities, calibration/adaptation controls, time- and mode-dependent behaviors, key performance aspects, and residual impairments (offsets, gain mismatches, jitter, noise, skew, supply noise, etc.)
Interface with digital design and verification teams to guarantee exhaustive model verification—ensuring all functionalities and edge-cases are included in regression and integration test plans
Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation)
Integrate behavioral models into modern verification environments (UVM, MS-MDV), utilizing assertion-based checks, analog/digital interface scoreboards, and power-aware techniques as appropriate
Optimize model implementations for simulation speed and accuracy
Drive continuous improvement and automation in the creation, maintenance, and validation of SerDes behavioral models
Establish and evangelize best practices and reusable frameworks for efficient, scalable RNM modeling and mixed-signal verification
Mentor and support teammates, sharing knowledge, methodology innovations, and documentation
Qualification
Required
BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience
Advanced proficiency with Verilog, SystemVerilog (including RNM, wreal modeling, and IEEE 1800-2012 SV-DC extensions)
Robust understanding of analog/mixed-signal SerDes sub-blocks: TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator
Proven ability to model analog circuit impairments: offsets, gain/mismatches, jitter, noise, skew, supply noise, etc
Fluency with analog schematics, SPICE-level simulation tools and waveform analysis
Strong scripting/programming in Python, TCL, Perl, C/C++
Familiarity with verification flows: regression, analog/mixed-signal co-simulation, digital verification, gate-level simulation, formal methods, and emulation
Experience with UVM testbenches, assertion-driven and coverage-driven verification
Company
Synopsys Inc
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products.
10001+ employees
H1B Sponsorship
Synopsys Inc has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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Trends of Total Sponsorships
2025 (177)
2024 (216)
2023 (158)
2022 (204)
2021 (215)
2020 (190)
Funding
Current Stage
Public CompanyTotal Funding
$2BKey Investors
NVIDIAGreen Pine Capital Partners
2025-12-01Post Ipo Equity· $2B
2022-09-21Post Ipo Equity
1994-01-01Post Ipo Equity
Leadership Team
Aart Geus
Co-Founder, Chairman & CEO
Chi-Foon Chan
President and co-Chief Executive Officer
Recent News
eeNews Europe
2025-12-30
Company data provided by crunchbase