Package Design Engineer jobs in United States
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UST · 2 months ago

Package Design Engineer

UST is a mission-driven company that transforms lives through technology. They are seeking a highly skilled Package Design Engineer to design and develop advanced multi-layer package substrates, ensuring compliance with manufacturing and assembly rules while collaborating with cross-functional teams and vendors.

ConsultingInformation ServicesInformation Technology
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H1B Sponsor Likelynote

Responsibilities

Perform the design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices
Perform package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA)
Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements)
Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability, warpage control) into package designs
Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations
Collaborate with Signal Integrity (SI), Power Integrity (PI), and thermal analysis teams to ensure robust performance
Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility
Provide on-site vendor support when required to resolve design and assembly issues

Qualification

EDA ToolsCadence AllegroFlip Chip DesignMulti-layer Substrate DesignSubstrate Manufacturing RulesCommunicationCollaboration Skills

Required

Bachelor's or Master's degree in Electrical Engineering, Electronics, Materials Science, or related field
5–8 years of hands-on experience in package design, with proven expertise in multi-layer (8+) substrate design
Proficiency with EDA tools: Mentor Graphics, Cadence Allegro, PLA. (Mentor Graphics Xpedition / Cadence Allegro Package Designer)
Strong knowledge of substrate manufacturing rules and assembly rules
Experience with Flip Chip package design methodologies
Familiarity with SI/PI/thermal considerations in advanced packages
Strong communication and collaboration skills for cross-functional and vendor engagement
Flexibility to travel and provide on-site vendor support as needed

Benefits

Full-time, regular employees accrue a minimum of 10 days of paid vacation per year
Receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year)
10 paid holidays
Are eligible for paid bereavement leave and jury duty
Eligible to participate in the Company’s 401(k) Retirement Plan with employer matching
Eligible for medical, dental, and vision insurance
Basic life insurance
Accidental death and disability insurance
Short- and long-term disability benefits
May purchase additional voluntary short-term disability benefits
Participate in a Health Savings Account (HSA)
Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines

Company

UST is a Digital Transformations Solutions Provider.

H1B Sponsorship

UST has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (870)
2024 (800)
2023 (647)
2022 (634)
2021 (612)
2020 (984)

Funding

Current Stage
Late Stage
Total Funding
$250M
Key Investors
Temasek Holdings
2018-06-27Private Equity· $250M

Leadership Team

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Krishna Sudheendra
CEO
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Alexander Varghese
Chief Administrative Officer & COO
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Company data provided by crunchbase