TSMC · 1 month ago
Advanced Defect Modeling and Testing (Technical Manager) (7101)
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$152K/yr - $244K/yr
15+ years expTSMC is the world’s leading semiconductor foundry, and they are seeking an experienced engineer to research advanced defect modeling and testing for next-generation semiconductor processes. The role focuses on developing methodologies for defect modeling, collaborating across teams, and shaping industry standards in advanced packaging technologies.
Consumer ElectronicsElectronicsManufacturingProduct DesignSemiconductor
Responsibilities
Develop defect models for 2D structures (standard cells, FEOL/MEOL/BEOL layers) and 3D structures such as TSVs, interconnects, hybrid bonding, and chip stacking
Perform root-cause analyses of electrical, mechanical, and thermal defects in advanced packages and address them using design-for-test methods
Conduct SPICE simulations to evaluate circuit behavior under defect conditions and identify failure scenarios
Use EDA ATPG tools (or develop internal methods) to generate defect-oriented test patterns
Assess the influence of probing techniques and test structure designs on defect detection and reliability learning
Develop and implement methodologies leveraging test/probe structures to monitor process variations and enhance yield
Collaborate closely with internal partners (DPT Standard Cell, PE/Fab, QR) and external partners (EDA vendors)
Implement advanced test methodologies for defect detection at both chip and package levels
Stay updated on evolving technologies and defect mechanisms in semiconductor manufacturing
Contribute to patents and publications in leading conferences and journals
Approximately 75% of this role will focus on fundamental research, with ~30% involving collaboration across design, process, and manufacturing teams
Qualification
Required
Education: Master's or Ph.D. in Computer Engineering, Semiconductor Physics, or a related field
Experience: At least 15+ years of expertise in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices, including 2D and 3D structures
Technical Skills: Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes. Programming or scripting skills (Python, Perl, C++) for automation and data analysis are required; experience with AI/ML for defect prediction is a plus
Domain Knowledge: Deep understanding of defect physics, testing/probing structures, and their impact on defect detection, characterization, and yield learning in advanced process nodes and 3D packaging. Familiarity with thermal and mechanical considerations in 3D integration
Industry Exposure: Demonstrated contributions through patents, publications, or conference presentations in defect modeling, reliability, or advanced packaging
Benefits
Market competitive pay
Allowances
Bonuses
Comprehensive benefits
Extensive development opportunities and programs
Company
TSMC
Established in 1987, TSMC is the world's first dedicated semiconductor foundry.
10001+ employees
H1B Sponsorship
TSMC has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (49)
2024 (27)
2023 (30)
2022 (17)
2021 (31)
2020 (35)
Funding
Current Stage
Public CompanyTotal Funding
$14.2BKey Investors
U.S. Department of CommerceBerkshire Hathaway
2024-04-08Grant· $6.6B
2024-01-01Acquired
2022-09-30Post Ipo Equity· $4.1B
Leadership Team
Morris Chang
Founder, Chairman & CEO
Peter M. Cleveland
Senior Vice President
Recent News
Channel NewsAsia
2026-01-12
2026-01-11
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