Northrop Grumman Australia · 1 month ago
Principal/ Senior Principal Digital ASIC Circuit Design Engineer
United States-Maryland-Annapolis Junction
Full-time
Onsite
Senior Level, Lead/Staff
$120K/yr - $180K/yr
5+ years expNorthrop Grumman is a leader in technological advancements, seeking a front-end ASIC design engineer to join their Advanced Processing Solutions Business. The role involves design and verification of full-custom digital circuits, requiring proficiency in Verilog and a strong understanding of synchronous digital design concepts.
Defense & Space
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Circuit behavioral coding in Verilog, System Verilog or VHDL RTL
Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools
Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL
Generating manufacturing test vectors and manufacturing circuit test plan
Help develop automated procedures to streamline digital design procedures
Qualification
Required
Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with STEM MS; 1 year with STEM Phd) for Principal level
Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus
Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board
Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with STEM related MS, 4 years with STEM related PhD) for Sr. Principal level
Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus
Preferred
Advanced Degree - either MS or PhD
Current security clearance or eligibility
Experience with chip level integration and ASIC chip lead - Strong design automation skills
Experience in CAD design network, tool configuration, and data management
Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)
Advanced Degree - either MS or PhD
Current security clearance
Experience with chip level integration and ASIC chip lead - Strong design automation skills
Experience in CAD design network, tool configuration, and data management
Benefits
Health insurance coverage
Life and disability insurance
Savings plan
Company paid holidays
Paid time off (PTO) for vacation and/or personal business
Company
Northrop Grumman Australia
Northrop Grumman Australia is the Australia-based arm of Northrop Grumman Corporation and committed to generating long-term prosperity, investing in advanced Research & Development, sovereign and exportable Intellectual Property, high-quality jobs and long-term technology leadership across the Commonwealth.
501-1000 employees
Funding
Current Stage
Late StageCompany data provided by crunchbase