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SpaceX · 2 days ago

FPGA/ASIC Engineer (Silicon Engineering)

Redmond, WA

Full-time

Onsite

Entry Level

$140K/yr - $170K/yr

1+ years exp

SpaceX is actively developing technologies to enable human life on Mars and is seeking a motivated FPGA/ASIC Engineer to work on the Starlink project. This role involves designing cutting-edge FPGAs and ASICs for deployment in space and ground infrastructures, contributing to the performance and capabilities of the Starlink network.

Advanced MaterialsAerospaceManufacturingNational SecuritySpace Travel

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog

Optimize designs for power, performance and area

Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation

Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab

Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification

Collaborate with software engineers in developing production software for your designs

Qualification

RTL DesignSystemVerilogVerilogASIC/FPGA integrationPythonC/C++BashEDA toolsAXI/AHB/APB protocolsElectrical engineering fundamentalsDebugging PCBsLearning new skillsMaster’s degreeTeam-playerCross-functional collaborationAdaptability

Required

Bachelor's degree in Physics, Electrical Engineering, Computer Engineering or Computer Science

1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

Must be willing to work extended hours and weekends as needed

Preferred

ASIC/FPGA system integration experience

Proficiency in Python, C/C++, and Bash

Experience in designing DSP, digital communication system datapath blocks, and/or modem design

Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)

Experience and understanding of AXI/AHB/APB protocols

Strong foundation in electrical engineering fundamentals

Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers

Ability to work in a dynamic environment with changing needs and requirements

Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis

Demonstrated ability to work in a highly cross-functional role

Enjoys being challenged and learning new skills

Master's in Electrical/Computer Engineering or related field