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Analog Devices · 4 months ago

Staff Engineer, Design Verification Engineering

US, CO, Colorado Springs, Chapel Hills

Full-time

Onsite

Senior Level, Lead/Staff

$119K/yr - $178K/yr

7+ years exp

Analog Devices, Inc. is a global semiconductor leader that focuses on bridging the physical and digital worlds. They are seeking a motivated design engineer for their Data Center & Energy team to provide support in design verification, working closely with a group of engineers on advanced mixed signal design verification techniques.

DSPElectronicsLightingSemiconductor

No H1B

U.S. Citizen Only

Responsibilities

Verification of mixed signal designs and sub-systems using leading edge verification methodologies

Contribute and influence the decisions on methodologies to be adopted for the verification

Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench in chip-level UVM environment and verify integration

Define testplans, tests and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage

Continuous interaction with analog and digital teams in enabling top-level chip verification

Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering team

Qualification

SystemVerilog/UVMDesign Verification infrastructureEDA toolsPythonVerilogC/C++Formal verification methodologyEnthusiasticInterpersonal skillsTeamworkCommunication skillsSelf-motivated

Required

Bachelor's or Master's degree in Electrical or Computer Engineering

7+ years of hands-on experience in SystemVerilog/UVM

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred

Experience in developing test benches using System Verilog and OVM/UVM

Knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog

Experience of pre and post-silicon verification test flow and automated test benches

Familiarity with verification on multiphase DC-DC controllers

Experience with verification of ARM/RISC-V based sub-systems or SoCs

Experience with verification of voltage interfaces like PMBUS, AVS, SVID, SVI3 etc

Experience with revision control systems like Perforce, Git etc

Verilog, C/C++, System C, TCL/Perl/Python/shell-scripting

RTL design/front-end design experience

Experience with analog SV-RNM/EE-net modeling

Experience with formal verification methodology

Strong interpersonal, teamwork and communication skills

Self-motivated and enthusiastic