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Northrop Grumman · 1 month ago

Principal/ Senior Principal Digital ASIC Circuit Design Engineer - R10215596

Linthicum Heights, MD

Full-time

Onsite

Senior Level, Lead/Staff

$120K/yr - $180K/yr

5+ years exp

Northrop Grumman is a leader in technological advancements and is seeking a Principal/Senior Principal Digital ASIC Circuit Design Engineer. The role involves designing and verifying full-custom digital circuits, utilizing various design tools, and collaborating with a team to develop innovative computing solutions.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Circuit behavioral coding in Verilog, System Verilog or VHDL RTL

Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools

Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL

Generating manufacturing test vectors and manufacturing circuit test plan

Help develop automated procedures to streamline digital design procedures

Qualification

VerilogSystem VerilogVHDLASIC design toolsStatic timing analysisCircuit synthesisFunctional verificationCommunication skillsTeam collaboration

Required

Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with STEM MS; 1 year with STEM Phd) for Principal level

Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with STEM related MS, 4 years with STEM related PhD) for Sr. Principal level

Experience with full product life cycle (requirements, design, implementation, test) of ASIC design

Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)

Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus

Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board

Strong written and oral communication skills

Preferred

Advanced Degree - either MS or PhD

Current security clearance or eligibility

Experience with chip level integration and ASIC chip lead - Strong design automation skills

Experience in CAD design network, tool configuration, and data management

Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre

Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)