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Axelera AI · 1 month ago

Staff Engineer - CPU & ISA Architecture (Europe based)

Austin, TX

Full-time

Hybrid

Lead/Staff

Axelera AI is a deep-tech startup creating a next-generation AI platform. They are seeking an experienced R&D engineer specializing in CPU architecture to evaluate architectural proposals and develop innovative improvements to meet AI training and high-performance computing needs.

AI InfrastructureArtificial Intelligence (AI)Machine LearningSemiconductorSoftware

Responsibilities

Design & Analysis: Research, design, and evaluate CPU microarchitectural components (pipelines, fetch/decode, branch prediction, caches, memory hierarchy, OoO/rename/issue, interconnects, SIMD/vector/matrix units). Analyze and optimize PPA trade-offs for AI, HPC, and cloud workloads

Modeling & Simulation: Build and validate performance/functional models, run simulations, and correlate results to RTL to guide architectural decisions

ISA Implementation: Develop and evaluate architectural extensions within RISC-V; assess their performance, programmability, and toolchain compatibility

Innovation & Prototyping: Propose, model, and prototype new mechanisms to improve efficiency, scalability, and performance

Collaboration & Research: Work closely with hardware, compiler, and system teams to align roadmaps and enable new capabilities. Stay ahead of trends in CPU, memory, interconnect, and AI-adjacent architectures

Qualification

CPU designISA extensionsPerformance modelingRTL designBenchmarkingLow-level softwareAnalytical skillsEnglish fluencyCollaborative skillsCommunication skills

Required

MS/PhD in CE/EE/CS (or related field) with focus on CPU architecture or microarchitecture

Deep expertise in CPU design (pipelines, memory systems, coherence, SIMD/vector/matrix units), PPA optimisation, and ISA extensions (RISC-V, ARM, x86)

Skilled in performance modeling and simulation (e.g., gem5, ChampSim, Sniper, QEMU), cycle-accurate and trace-driven analysis, and correlation to RTL

Experienced in benchmarking and workload characterisation (SPEC, MLPerf, or internal suites)

Proficient in RTL design and validation (Verilog/SystemVerilog/Chisel), including simulation, synthesis, and FPGA/emulation bring-up

Knowledge of compiler/toolchain integration, low-level software (C/C++/assembly), Linux kernel/driver development, and performance tuning for ISA features

Strong analytical, collaborative, and communication skills with proven ability to drive architectural proposals from concept to validation

Fluent in English

Able to work from one of our European offices or remotely, preferably based in Bavaria (Munich), Belgium, or Italy