Flux Computing · 1 month ago
Senior / Staff Digital Design Engineer
San Francisco, CA
Full-time
Onsite
Senior Level, Lead/Staff
$194K/yr - $270K/yr
7+ years expFlux Computing is seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design. The role involves end-to-end ownership of high-speed, real-time data-processing silicon and requires collaboration with multidisciplinary teams to create next-generation OTPUs.
Artificial Intelligence (AI)HardwareMachine LearningManufacturingOptical Communication
Responsibilities
Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification
Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets
Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions
Mentor junior engineers, lead design reviews and champion best‑practice design methodologies
Qualification
Required
7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream
Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)
Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation
Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab
Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation
Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics
Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment
Preferred
Tape-out experience at 22 nm or below
Knowledge of coherent optical links or photonic-electronic co-design
Familiarity with AI/ML workloads, systolic arrays or tensor-processing architectures
Contributions to open-source RTL, verification frameworks or FPGA boards
Benefits
$800/month health insurance stipend
100% of the employee premium covered once the group policy is live
Options like dental, vision and life insurance
Access to a 401(k) retirement savings plan
Employer match in line with tech market norms
Top of the line, high-spec tech for everyone
Sony noise-cancelling headphones and ergonomic setups
Personal company card for tools
Periodic travel to London HQ
Regular team socials
33 days of paid time off (PTO), including US federal holidays
Company
Flux Computing
Flux Computing designs optical AI accelerators that use light-based processors for training and inference on large models.
51-200 employees
Funding
Current Stage
Growth StageCompany data provided by crunchbase