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Marvell Technology · 22 hours ago

Design Verification Intern - Master's Degree

Westborough, MA

Internship

Onsite

Intern

$30/hr - $59/hr

Marvell Technology is a leading provider of semiconductor solutions that are essential for data infrastructure. The Design Verification Intern will work closely with an RTL engineer to verify chip designs, ensuring they meet customer specifications through simulation and debugging.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Verify all of the circuitry that goes inside our chips for the general market and for specific customers

Use System Verilog to debug designs in Verilog

Run simulations using Synopsys VCS or a similar program, and then debug as needed until the design meets required specifications

Work closely with DFT engineers who are working in parallel on your blocks

Attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues

Take responsibility for larger blocks, and present to a review committee to explain your test plan and test schedule for those larger blocks

Qualification

VerilogSystem VerilogSimulation toolsLinux environmentPython scriptingTeam communicationDetail-oriented

Required

Be currently pursuing your Bachelor's or Master's degree in Electrical Engineering or related field

Your coursework must have included some logic design, Verilog or VHDL, basic circuits, and computer architecture

You should have a focus in VLSI or show projects in your courses that directly relate to chip design

You have used a tool like Synopsys, Cadence, or Mentor to run simulations and you can write and debug a testbench

Be comfortable working in a Linux environment and doing scripting with Python

Be extremely detail-oriented and ready to iterate a design over and over again until it is refined completely

Work and communicate well with your team, keeping them in the loop about your progress, issues you encounter, and any deviations from the planned schedule