Innatera · 4 months ago
Staff Digital Design Engineer - CPU Architecture & RISC-V
Innatera is a rapidly growing Dutch semiconductor company that develops ultra-efficient neuromorphic processors for AI at the edge. They are seeking a Staff Digital Design Engineer to take technical ownership of RISC-V-based CPU architecture and subsystem integration in their next-generation neuromorphic SoCs, leading design and implementation efforts while collaborating closely with various teams.
AI InfrastructureArtificial Intelligence (AI)Machine LearningSemiconductor
Responsibilities
Design and architect advanced CPU cores and micro-architectures, with particular expertise in RISC-V instruction sets and extensions
Translate high-level architectural requirements into detailed micro-architectural specifications for CPU designs
Collaborate with verification engineers to ensure comprehensive testing and validation of CPU IP, including instruction set compliance and performance
Define and implement SoC-level architectures, specifically focusing on the integration of CPU cores and their interaction with other IP and subsystems
Assist in verifying SoC functionality through top-level testing, ensuring robust system performance, especially regarding CPU operation
Perform RTL coding and debugging of CPU cores and related logic using Verilog or System Verilog
Conduct RTL and gate-level simulations to ensure design accuracy and performance for CPU and associated logic
Execute all front-end design tasks for CPU cores, including synthesis, STA, formal equivalence checking
Support software-hardware co-design efforts, demonstrating a deep understanding of the SW-HW system and its interaction with the CPU
Drive the development of innovative CPU IP concepts based on high-level product specifications, exploring new architectural paradigms
Evaluate, customize, and integrate third-party CPU IP or components (e.g., memory management units, interrupt controllers) to enhance system performance
Work closely with analog design, verification to ensure seamless integration and cohesive project development for CPU-centric designs
Qualification
Required
7+ years of experience in digital design, with a strong focus on CPU architecture and micro-architecture development
Demonstrable experience in designing and implementing RISC-V based CPU cores (e.g., custom cores, modifications to open-source cores)
Deep understanding of CPU pipeline stages, memory hierarchies (caches, MMU), interrupt handling, and bus interfaces related to CPU design
Expertise in RTL coding (Verilog/System Verilog) and debugging for complex digital modules, particularly CPU designs
Strong knowledge of SoC architecture and subsystem integration, specifically concerning CPU integration
Proven experience in front-end design tasks for CPU cores, including synthesis, STA, and formal equivalence checking
Solid understanding of digital verification methodologies and working collaboratively with verification teams, with a focus on CPU verification
Familiarity with common communication protocols (e.g., AMBA AXI/AHB) relevant to CPU-to-system interfaces
Strong problem-solving skills with great attention to detail, particularly in the context of complex CPU architectures
Excellent communication and collaboration abilities, particularly in cross-functional team environments
A proactive and self-motivated attitude toward learning and innovation, especially in the evolving landscape of CPU design and RISC-V
Benefits
Competitive salary
Pension plan
Ambitious team with the freedom to innovate
A flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme)
An inclusive company culture that embraces open communication, diversity and supports holistic personal development
Compensation for commuting to the office, fruits, drinks and snacks in the office
Company
Innatera
Innatera is a developer of ultra-low-power intelligence for sensors.
Funding
Current Stage
Growth StageTotal Funding
$27.25MKey Investors
Invest-NLIntel Ignite
2024-06-27Series A· $5M
2024-03-19Series A· $16.29M
2021-11-19Non Equity Assistance
Recent News
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2026-01-06
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