Lead Analog SerDes Architect/Design Engineer jobs in United States
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Intel Corporation · 1 month ago

Lead Analog SerDes Architect/Design Engineer

Intel Corporation is driving the future of high-speed connectivity for data centers through cutting-edge silicon photonics integration. They are seeking a Lead Analog SerDes Architect / Design Engineer to define circuit architecture and enable designs for next generation optical interconnects, collaborating with other designers and providing guidance to junior team members.

Semiconductors
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Growth Opportunities
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Responsibilities

Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications
As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development
Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers
Plan design work with constraints on performance, schedule and quality
Provide guidance to junior designers and layout engineers
Guidance to develop test plans for post-silicon characterization
Document all design work with review materials and detailed design descriptions

Qualification

Analog CMOS/BiCMOS designSerDes circuit designMixed-signal design flowHigh-speed serial linksOptical communicationsGuidance to junior designersTeam collaborationDocumentation skills

Required

Minimum of MS in Electrical Engineering
8+ years of experience in high-speed serial links
Deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies
Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates
Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers
Experience with design of precision analog circuits like ADC/DACs
Experience with designing PAM4/NRZ links
Experience with Mixed signal design flow
Experience with full-chip designs, ESDs and verification flows

Preferred

Familiarity with Optical communications
Experience with 400G/800G/1.6T optical links
Experience with package/test setup design

Benefits

Competitive pay
Stock
Bonuses
Health
Retirement
Vacation

Company

Intel Corporation

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