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BAE Systems, Inc. · 1 day ago

FPGA Design Manager / Section Lead

Nashua, NH

Full-time

Hybrid

Senior Level, Lead/Staff

$147K/yr - $249K/yr

10+ years exp

BAE Systems is seeking FPGA Design Managers to lead an FPGA Design group within their Electronic Systems business area. The role involves managing a team of engineers, advancing FPGA design practices, and influencing program execution while mentoring less experienced team members.

Defense & Space

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Leading and managing a team of FPGA Design engineers

Hiring and staffing design engineers in support of program needs

Advancing the state of FPGA design at BAE Systems by assessing and evaluating modern tools, design techniques, and hardware resources

Managing personnel performance and development

Influencing program execution, and scope management

Communicating information to engineering team, up through leadership, and across the organization for sharing of best practices and lessons learned

Assisting in the development, review, and approval of proposals, and negotiating scope with programs

Enhancing engineering processes used on programs, and ensuring consistent application of those processes

Supporting key initiatives to improve the business execution or discipline

Qualification

FPGA design experienceFPGA/ASIC developmentLeadership skillsProject managementVHDL codingVerilog HDL codingFPGA architectureMS-Project proficiencyFlexibility in dynamic environmentScripting skillsDoD projectsCommunication skillsMentorship ability

Required

10+ years of relevant experience with bachelor's degree in EE/ECE

Current Security Clearance (Secret or higher), or eligible to obtain one

Experience leading and managing FPGA/ASIC design teams

Proficient in planning and managing schedule, staffing, cost, and risks

Flexibility to work in a dynamic environment with changing needs, requirements, and technical challenges

Ability to provide mentorship to less experienced team members

Strong written and oral communication skills

Deep understanding of FPGA architecture and design tradeoffs

Experienced in all stages of FPGA and/or ASIC development including requirements management, RTL design, synthesis, timing analysis, lab bring up/validation

Proficient in VHDL (preferred) or Verilog HDL coding

Familiarity with AMD (Xilinx) Vivado or Altera (Intel) Quartus

Proficient in MS-Project, MS-Word, MS-Excel