Ayar Labs · 9 hours ago
Principal Engineer, ASIC Design Verification
San Jose, CA
Full-time
Onsite
Lead/Staff
$180K/yr - $230K/yr
12+ years expAyar Labs is revolutionizing computing by moving data with light and is seeking a Principal Design Verification Engineer to lead the verification strategy for their next-generation silicon photonic chip. The role involves architecting scalable verification environments, driving high-quality silicon from concept to tape-out, and mentoring a team of engineers.
Artificial Intelligence (AI)ComputerHardwareInformation TechnologySemiconductor
Responsibilities
Architect Testbenches: Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and Sub-systems
Drive Methodology: Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows
Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability
Complex Debugging: Lead the effort to debug elusive hardware bugs, root-causing issues across RTL, firmware, and the verification environment
Technical Leadership: Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence
Automation & Efficiency: Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure
Qualification
Required
MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification
Expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology)
Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.)
Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe)
Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell)
Experience defining functional coverage groups and driving logic verification to 100% closure
Preferred
Experience with formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions)
Hands-on experience with hardware emulation platforms
Familiarity with RISC-V or ARM architecture and coherency protocols
Experience in Analog/Mixed-Signal (AMS) verification
Experience with C/C++ or SystemC modeling for reference models
Experience working on digital designs with multiple clock domains and clock dividers
Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
Experience with verification of HBM memory interfaces (PHY and controller)
Experience in formal model equivalence checking tools and verification methodology
Programming experience in Python
Company
Ayar Labs
Ayar Labs develops optical I/O solutions for large-scale AI workloads to accelerate data movement within AI systems.
51-200 employees
H1B Sponsorship
Ayar Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (14)
2024 (2)
2023 (7)
2022 (4)
2021 (4)
2020 (2)
Funding
Current Stage
Late StageTotal Funding
$374.65MKey Investors
Capital TENBoardman Bay Capital ManagementLockheed Martin Ventures
2024-12-11Series D· $155M
2023-05-24Series C· $25M
2022-04-26Series C· $130M
Leadership Team
Mark Wade
President and CEO, Co-Founder
Alex Wright-Gladstein
Co-Founder and Advisor
Recent News
2025-11-23
2025-11-19
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