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Meta · 20 hours ago

ASIC Engineer, Physical Design

Austin, TX

Full-time

Onsite

Senior Level

$146K/yr - $209K/yr

6+ years exp

Meta is hiring ASIC Physical Design Engineers within their Infrastructure organization. The role involves developing and owning physical design implementation for low-power and high-performance designs, as well as resolving design and flow issues related to physical design.

Computer Software

Comp. & Benefits

Responsibilities

Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes

Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution

Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs

Define and implement schemes, including semi-custom placement and routing, to improve performance and power

Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle

Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO’s

Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality

Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions

Qualification

Physical design implementationTiming closureEDA toolsProgramming/scriptingLow power implementationFloor planningClock distributionStatic timing analysisInterpersonal skillsTeamworkCommunication skills

Required

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

6+ years of experience in interpersonal, teamwork, communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors

Experience in physical design and timing closure

Experience with large SOC designs (>20M gates) with frequencies over 1GHZ

Experience in floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs

Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre

Programming/scripting skills: TCL, Python, Perl or Shell

Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies

Knowledge of geometry/process/device technology implications on physical design

Preferred

Experience in full chip floor planning, partitioning, budgeting, and power grid planning

Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge

Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques

Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions

Knowledge of Circuit design, device physics, and sub-micron technology

Experience in the physical design of data-path intensive designs

Experience in the 3D-IC technology, methodology, and advanced packaging

Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC