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Northrop Grumman · 1 month ago

Staff Lead Design Verification Engineer - R10216127

Annapolis Junction, MD

Full-time

Onsite

Lead/Staff

$188K/yr - $282K/yr

10+ years exp

Northrop Grumman is a leading company in technological advancements, seeking a Staff Lead Design Verification Engineer to develop high-performance computing systems. The role involves leading the verification team for digital logic, ensuring compliance with design specifications, and mentoring junior engineers.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Create comprehensive test-benches for behavioral simulation

Design and implement verification strategies for complex digital systems

Ensure RTL implementation meets precise design specification requirements

Conduct in-depth behavioral simulations across ASIC and FPGA

Generate and execute advanced UVM Test cases

Achieve 95% code coverage goals and functional coverage across critical metrics

Perform detailed code coverage analysis, including: (Statement coverage, Expression coverage, Branch coverage, Toggle coverage)

Utilize both functional and timing simulation tools

Verify logical behavior and implementation accuracy

Identify and resolve signal delay and performance issues in gate timing requirements

Develop comprehensive Universal Verification Methodology (UVM) simulation environments

Work closely with design teams to validate RTL implementations

Provide detailed feedback and recommendations for design improvements

Participate in design reviews and Lead in verification planning

Mentor junior verification engineers

Contribute to continuous improvement of verification methodologies

Qualification

Functional VerificationHardware Description LanguagesUniversal Verification MethodologyBehavioral SimulationEDA ToolsCode Coverage StrategiesContinuous ImprovementTeam LeadershipMentoring

Required

Bachelor's degree in Computer Engineering, BSEE, or comparable STEM Degree and 12 years industry experience in a design verification role or Master's Degree plus 10 years experience or PhD plus 7 years experience

Experience with functional verification methodology for the full life cycle of products with leading a team with various levels of experience and skills

Demonstrated experience leading Verification Teams

Specialized experience in functional verification with multiple Tape Outs

Expert-level proficiency in Hardware Description Languages: (Verilog, VHDL, SystemVerilog)

Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage strategies)

Extensive experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)

Extensive experience with verification methodologies: Universal Verification Methodology (UVM)

Regression and automation framework development

This position requires the applicant to be a U.S. citizen

Candidates must be willing to obtain and maintain a security clearance