ASIC/FPGA Principal Verification Engineer VI jobs in United States
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Lockheed Martin · 1 month ago

ASIC/FPGA Principal Verification Engineer VI

Lockheed Martin is a leading technology innovation company focused on solving the world's most complex challenges. They are seeking a Principal Verification Engineer to lead the verification and validation processes for ASICs, FPGAs, and SOCs, while mentoring team members and driving improvements in efficiency and effectiveness.

AerospaceCyber SecurityMachinery ManufacturingMilitaryNational SecurityRemote SensingSecurity
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Growth Opportunities
badNo H1BnoteSecurity Clearance RequirednoteU.S. Citizen Onlynote

Responsibilities

Serve as the Principal Subject Matter Expert (SME) regarding verification and validation for the department
Develop roadmaps and processes related to verification and validation of complex devices
Develop and promote strategies and techniques that scale from low-level to system-level to improve cost and timelines
Mentor others in the best practices of verification and validation
Continuously assess new tools and methodologies related to verification and validation, presenting findings, making recommendations, and training others
Work closely with both design and verification teams to develop cohesive solutions
Develop business cases that support verification and validation improvements
Support all aspects of ASIC, FPGA, and SOC development, to include architecture, design, and analysis
Support technical reviews, and present to internal and external stakeholders

Qualification

FPGA verificationASIC verificationUVM methodologyHDL programmingSoC designMentoring engineersTest case developmentCoverage analysisSpace-grade knowledgeHardware emulationProject managementTechnical presentations

Required

Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education
12+ years of professional experience
Experience in verification of FPGA and ASIC devices utilizing modern verification methodologies such as UVM
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)
Willing and able to obtain and maintain a DoD Top Secret clearance, thus you are a US Citizen

Preferred

Experience leading projects of multiple engineers, managing schedules, prioritizing work and actively communicating with internal or external stakeholders
Experience working closely with SoC design and cross functional teams to refine requirements and fully define the verification plan for complex FPGA's and ASIC's
Experience in driving process advancement and program reviews
HDL programming experience with VHDL, SystemVerilog, and/or Verilog
Experience architecting advanced testing environments for complex SoC's and multiple chip designs leveraging multiple verification strategies as appropriate, including UVM/SystemVerilog, emulation, formal verification and lab based techniques
Experience developing test cases based off given requirements
Experience building test benches for FPGA / ASIC designs to provide randomized stimulus
Experience identifying and implementing necessary test exclusions
Experience analyzing coverage results generating coverage reports (code and functional)
Experience mentoring and training other engineers
Experience presenting to customers and executive leadership
Knowledge of space-grade/qualified FPGAs and ASICs
Experience or coursework in hardware emulation (ZeBu, Palladium, etc.)
Experience or coursework in older verification methodologies including OVM or VMM

Benefits

Medical
Dental
Vision
Life Insurance
Short-Term Disability
Long-Term Disability
401(k) match
Flexible Spending Accounts
EAP
Education Assistance
Parental Leave
Paid time off
Holidays

Company

Lockheed Martin

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Lockheed Martin is a global security and aerospace company that specializes in advanced technology systems, products, and services. It is a sub-organization of Lockheed Martin.

Funding

Current Stage
Public Company
Total Funding
$6.06B
Key Investors
Air Force Research Laboratory
2025-12-05Post Ipo Debt· $3B
2025-08-28Post Ipo Debt· $3B
2023-11-13Grant· $33.7M

Leadership Team

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Jim Taiclet
Chairman, President & CEO
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Craig Martell
Chief Technology Officer
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Company data provided by crunchbase