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Acceler8 Talent · 3 weeks ago

Principal Design Verification Engineer - AI Data Center Chips

San Francisco Bay Area

Full-time

Hybrid

Lead/Staff

$250K/yr - $350K/yr

Acceler8 Talent is partnering with a well-funded startup to hire an experienced Top-Level Design Verification Engineer. This role involves owning verification execution at subsystem and chip-level for a high-performance data center chip, focusing on developing methodologies and leading verification activities.

Staffing & Recruiting

Hiring Manager

Drew Cummings

Responsibilities

Help define and refine verification methodologies that scale from individual blocks to subsystems, full-chip environments, and system-level validation

Take ownership of verification activities at the subsystem and chip levels, developing testbenches, test suites, and supporting infrastructure to achieve both functional and structural coverage goals

Lead the planning and execution of verification reviews, including test plan assessments, progress updates, and closure evaluations, ensuring readiness for key silicon milestones such as design freeze and tapeout

Qualification

End-to-end verificationSystemVerilogUVMPythonC/C++Microarchitecture understandingScripting languagesFormal verificationSimulation-based verificationEmulation familiarityFPGA prototypingSilicon bring-up

Required

Proven end-to-end verification experience, taking designs from architectural or specification-level definition all the way through to production silicon

Proficiency in SystemVerilog along with scripting and programming languages such as Python, C/C++, Bluespec, or similar tools used for verification and silicon modeling

Demonstrated use of modern verification frameworks including UVM and assertion-based methods; strong skills in both formal and simulation-based verification are essential

Experience developing reusable tests, drivers, and infrastructure that can transition seamlessly into silicon validation and post-silicon debug workflows

Solid understanding of microarchitecture and design principles for high-performance compute systems (CPUs, GPUs, accelerators), high-speed interconnects, memory subsystems, and related components