Marvell Technology · 2 weeks ago
Senior Principal Digital IC Design Engineer
Irvine, CA
Full-time
Onsite
Senior Level, Lead/Staff
$190K/yr - $281K/yr
10+ years expMarvell Technology is a leading provider of semiconductor solutions that are integral to data infrastructure. The Senior Principal Digital IC Design Engineer will be part of the R&D team, focusing on designing hardware for datacenter and AI SOCs, collaborating with various teams to ensure high-quality hardware production.
DSPInternet of ThingsManufacturingSemiconductorWireless
No H1B
U.S. Citizen Only
Responsibilities
Define the micro-architecture of PCIe/CXL subsystems for our customers
Work closely with the architecture, floor planning, backend, verification, DFT, STA teams, and other cross-functional teams to produce the highest quality hardware
Develop and write micro-architectural specifications of the design
Implement designs using good RTL coding and low power techniques
Collaborate with the backend team to close on synthesis, place and route, and timing signoff
Collaborate with the verification team on pre-silicon verification tasks such as reviewing test plans, coverage closure, and full-chip simulation debug
Plan, scope, and time tasks with the project manager
Work with post post-silicon group to resolve any lab issues and successfully bring up silicon
Collaborate with the software team to ensure customer use cases requirements are met
Qualification
Required
Bachelor's degree in computer science, Electrical Engineering, or related fields, and 15+ years of related professional experience
Or a Master's degree in computer science, Electrical Engineering, or related fields with 12+ years of experience
Or a PhD in Computer Science, Electrical Engineering, or related fields with 10+ years of experience
Expertise in PCIe/CXL architecture
Expertise in micro architecture and translating requirements into design
Expertise in interacting with 3rd party IP vendors and customers
Expertise in System Verilog RTL coding techniques
Familiar with modern PCIe and SoC architectures and various interface technologies such as AXI, CXL, IDE, TDISP, ATS, LTSSM, VDM, and MSI-X
RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification
Experience in implementation/timing closure for high-speed design
Preferred
Hands-on experience for all aspects of the chip-development process, with proficiency in front-end design tools and methodologies, is a plus
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable
Benefits
Flexible time off
401k
Year-end shutdown
Floating holidays
Paid time off to volunteer
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
Recent News
2026-01-12
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2026-01-11
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