Marvell Technology · 1 day ago
Senior Staff Digital Design Engineer – Wireline PHYs
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
$124K/yr - $186K/yr
7+ years expMarvell Technology is a leader in semiconductor solutions that are integral to data infrastructure. The Senior Staff Digital Design Engineer will focus on system-level digital design and integration of wireline PHY IP for high-performance SoCs and ASICs, responsible for architecting and implementing digital control and DSP logic within larger system architectures.
DSPInternet of ThingsManufacturingSemiconductorWireless
Responsibilities
Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP targeting SerDes, Die-to-Die, and Parallel Optics applications
Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control
Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments
Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals, including DSP and datapath optimizations
Support system bring-up activities, validation planning, and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic
Mentor junior engineers and contribute to improving design methodologies for PHY system integration, including DSP and datapath design best practices
Qualification
Required
Master's degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields
Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols
Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels
Deep knowledge of CDC and RDC design principles
Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers, including interrupt and event handling
Familiarity with scripting for design automation (Python, TCL, Perl)
Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components
Preferred
Understanding of firmware-hardware co-design and system bring-up tools
Benefits
Flexible time off
401k
Year-end shutdown
Floating holidays
Paid time off to volunteer
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
H1B Sponsorship
Marvell Technology has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (242)
2024 (186)
2023 (154)
2022 (210)
2021 (210)
2020 (165)
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
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