Qualcomm · 1 month ago
RTL-Synthesis CAD Engineer
San Diego, California, United States of America
Full-time
Onsite
Entry, Mid Level
$98K/yr - $148K/yr
1+ years expQualcomm Technologies, Inc. is seeking a RTL-Synthesis CAD Engineer to join their Global CAD team. The role involves developing RTL and Synthesis solutions for Snapdragon chips, requiring expertise in SystemVerilog and CAD development to enhance implementation tools and methodologies.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Participating to the development of Qualcomm RTL Optimization engine and methods, leveraging both design analytics and GenAI techniques
Improving the SoC Synthesis and DFT Stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips
Enabling new features from EDA tools or/and internal tools for RTL PPA, RTL Analysis, Synthesis and DFT Stitch
Support Snapdragon design teams on CAD solutions, analyze their requests, and address their requests through ticket queues
Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement
Setting up, augmenting, and maintaining a regression of complex RTL Opt and Synthesis testcases
Innovating with design/tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents
Participate to Synthesis and DFT Stitch flows enablement for foundry advanced process nodes
Participate to the tuning of design recipes at RTL Opt and Synthesis levels to address specific objectives such as area, turn-around time on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP
Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of die area reduction, dynamic power, performance and turn-around time
Participate to the specification of new CAD solutions addressing the PPA requirements of the design teams, in the RTL Opt and Synthesis domains
Deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, DFT stitch failures etc
Interface and drive EDA vendor Application Engineers on the resolution of block convergence problems faced by the Snapdragon design teams
Qualification
Required
Bachelor's degree in Science, Engineering, or related field
SystemVerilog knowledge
Synthesis or/and Place and Route exposure
CAD development skills to define and develop implementation tools and methodologies for PPA
Ability to shorten design cycle time
Experience in close collaboration with Snapdragon Design and Implementation teams
Experience with leading edge internal and EDA technologies in the Implementation domain
Experience in developing good-by-construction automation and PPA recipes for complex designs
Ability to participate in the development of Qualcomm RTL Optimization engine and methods
Ability to improve SoC Synthesis and DFT Stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips
Ability to enable new features from EDA tools or/and internal tools for RTL PPA, RTL Analysis, Synthesis and DFT Stitch
Ability to support Snapdragon design teams on CAD solutions, analyze their requests, and address their requests through ticket queues
Ability to interface with EDA vendors to enable production-ready tool sets that satisfy project's requirement
Ability to set up, augment, and maintain a regression of complex RTL Opt and Synthesis testcases
Ability to innovate with design/tool/flow techniques for area reduction, dynamic power reduction and turn-around time
Ability to participate in patents
Ability to participate in Synthesis and DFT Stitch flows enablement for foundry advanced process nodes
Ability to participate in the tuning of design recipes at RTL Opt and Synthesis levels
Ability to participate along with Qualcomm talented AI team to R&D initiatives driving differentiation
Ability to participate in the specification of new CAD solutions addressing the PPA requirements of the design teams
Ability to deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, DFT stitch failures
Ability to interface and drive EDA vendor Application Engineers on the resolution of block convergence problems
Preferred
Bachelor of Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field
1-4 years of experience in VLSI CAD, preferably RTL analysis, Synthesis, DFT
1-4 years of experience with scripting tools and programming languages: Python and TCL preferred
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
Recent News
2026-01-17
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