Cadence ยท 15 hours ago
Design Engineering Director
San Jose, CA
Full-time
Onsite
Director/Executive
$178K/yr - $332K/yr
10+ years expCadence is a company that hires and develops leaders and innovators in technology. The Design Engineering Director will lead the organization responsible for characterizing and validating Analog and Digital IP based Silicon Solutions, while managing a team and coordinating with various departments to ensure timely results.
AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
Responsibilities
Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence
Manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities
Coordinate with R&D, Marketing teams in defining the scope and delivering the results in time
Develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon
Architect and design Printed circuit boards in Schematic and layout level
Develop lab automation scripts and test result analysis to debug and root cause silicon failures
Develop ESD/Latchup/HTOL tests to meet industry standards reliability qualification & specification
Qualification
Required
10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing
2-3 years of management experience leading/mentoring a small team of engineers
Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers
Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard's specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon
Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize
Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements
Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures
Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification
Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++
Preferred
Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus
Benefits
Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
A variety of medical, dental and vision plan options
And more
Company
Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
10001+ employees
H1B Sponsorship
Cadence has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (306)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO
Leadership Team
Paul Cunningham
Senior Vice President and General Manager
Tom Beckley
Senior Vice President, Custom IC & PCB Group
Recent News
2026-01-07
2026-01-06
Company data provided by crunchbase