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AMD · 3 days ago

Power Methodology Engineer, Data Center Hardware IPs

Santa Clara, CA

Full-time

Onsite

Senior Level

$191K/yr - $287K/yr

AMD is a leader in building great products that accelerate next-generation computing experiences. They are seeking a senior power lead for power architecture solutions, specializing in optimizing power efficiency and performance for microprocessors, GPUs, and machine learning accelerators.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications

Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption

Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs

Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications

Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)

Analysis and modeling: Creating power models and scripts for performance/power trade-offs

Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency

Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack

Leadership: Mentoring junior team members and providing technical leadership on complex projects

Qualification

Power management algorithmsPower analysis toolsLow-power processor architectureASIC/SoC optimization techniquesMachine learning conceptsVerilogVHDLPython scriptingAnalytical skillsProblem-solving skillsCommunication skillsLeadership skills

Required

A senior power lead for power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance

Creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle

Passion for modern, complex processor architecture, digital design, and verification

Excellent communication skills and experience collaborating with other engineers located in different sites/time zones

Strong analytical and problem-solving skills and are willing to learn and ready to take on problems

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications

Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs

Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications

Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)

Creating power models and scripts for performance/power trade-offs

Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency

Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack

Mentoring junior team members and providing technical leadership on complex projects

Preferred

Extensive industry experience, with a specialization in low-power-processor architectures or power management

Expertise in ASIC/SoC power analysis and optimization techniques

Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)

Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics

Proficiency in hardware description languages like Verilog or VHDL, and scripting

Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)

Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools

Strong scripting and automation skills, preferably in Python

Excellent communication, presentation, and leadership skills to drive projects and collaborate effectively with cross-functional teams