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Marvell Technology · 1 day ago

Senior Principal Memory Architect

Santa Clara, CA

Full-time

Onsite

Senior Level, Lead/Staff

$177K/yr - $266K/yr

8+ years exp

Marvell Technology is a leading semiconductor solutions provider focused on data infrastructure. The Senior Principal Memory Architect will define and deliver memory subsystem solutions that power advanced data center architectures, collaborating with various teams to innovate and ensure product quality.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Hiring Manager

Jeff Shiverdaker

Responsibilities

Architect high-performance HBM/DDR memory subsystems for Marvell’s custom compute products, including developing specifications, performance models, and product requirements

Define and evolve Marvell’s memory controller architecture strategy and roadmap, partnering with customers and internal teams to deliver optimal solutions for next-generation workloads

Drive micro-architecture development, design specifications, and verification plans in close collaboration with RTL, physical design, and validation teams

Develop system-level models to evaluate and optimize performance (throughput, latency, QoS, power, area) across multiple design options

Collaborate cross-functionally with hardware, firmware, and validation organizations to ensure end-to-end product quality, performance, and reliability

Lead innovation initiatives around memory subsystem architecture, including ECC, RAS, and reliability improvements for server-class products

Represent Marvell in technical discussions with customers and ecosystem partners, influencing industry direction and technical decisions

Qualification

HBM/DDR memory architectureMemory controller designJEDEC standardsSystem modeling toolsECCRAS featuresAnalytical thinkingCommunication skillsCollaboration skills

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of relevant experience, or Master's/PhD with 8+ years of experience in memory architecture or system design

Deep understanding of DDR/HBM memory subsystem architecture for data center compute, AI, or XPU systems

Proven experience designing or specifying HBM/DDR memory controllers and associated subsystems

Strong familiarity with JEDEC standards (HBM3/4, DDR4/5, LPDDR5/5X/6) and related memory interface technologies

Experience with system modeling and performance analysis tools for evaluating memory system trade-offs

Demonstrated experience developing ECC, RAS, and reliability features for server or high-performance SoC designs

Strong analytical and conceptual thinking with a track record of innovation

Excellent communication skills and the ability to collaborate effectively across global, multi-disciplinary teams

Passion for architecting memory solutions that redefine performance and efficiency in data center computing