Marvell Technology · 13 hours ago
Senior Principal Digital IC Design Engineer
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
$169K/yr - $253K/yr
10+ years expMarvell Technology is a leader in semiconductor solutions that connect the world through data infrastructure. The Senior Principal Digital IC Design Engineer will contribute to the development of hardware solutions, focusing on designing and implementing ASICs for industry-leading customers, while collaborating with various teams and mentoring junior engineers.
DSPInternet of ThingsManufacturingSemiconductorWireless
No H1B
U.S. Citizen OnlyHiring Manager
Magda Melena
Responsibilities
Collaborate with systems and architecture teams to define SoC-level specifications, including performance, power, area, and feature requirements
Translate high-level product requirements into detailed micro-architecture specifications for subsystems and IP blocks
Lead RTL development and integration, ensuring modularity, reusability, and compliance with design guidelines
Create modular and reusable design components to support scalable and maintainable architectures
Partner with DV teams to define and review verification plans, including functional, coverage-driven, and power-aware strategies
Support pre-silicon bring-up activities, including FPGA prototyping and emulation
Support post-silicon validation, working closely with lab teams to resolve complex issues and validate performance targets
Conduct detailed design reviews with cross-functional teams and contribute to the continuous improvement of design and verification methodologies
Supervise and mentor junior digital design engineers, providing technical leadership and guidance
Qualification
Required
Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 15+ years of professional experience, or Master's/PhD in Computer Science, Electrical Engineering, or related fields with 10+ years of experience
Minimum of 10 years of industry experience in developing, implementing, and testing high-performance communications ASIC products
Extensive experience in RTL design, including verification, synthesis, and timing closure
Strong background in embedded microcontroller systems
Proficiency with UNIX-based EDA tools (e.g., VCS, PrimeTime, Design Compiler, CDC) and deep understanding of ASIC design flows
Familiarity with PHY/MAC layer communication protocols such as Ethernet, PCIe, UA Link, SUE, or ESUN
Proven track record in project leadership, with the ability to thrive in a fast-paced, dynamic environment and manage multiple priorities effectively
Preferred
Knowledge of signal processing circuit structures or error-correcting code architectures is a plus
Experience with industry-standard interfaces such as MDIO, I2C, I3C, SPI, and SMBus is a plus
Benefits
Flexible time off
401k
Year-end shutdown
Floating holidays
Paid time off to volunteer
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
Recent News
2026-02-03
Morningstar.com
2026-02-02
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