Altera · 7 hours ago
Design Verification Engineer
San Jose, CA
Full-time
Onsite
Mid, Senior Level
$114K/yr - $165K/yr
3+ years expAltera is a leading FPGA company focused on accelerating programmable compute in various domains. They are seeking a Sr Silicon Design Verification Engineer to perform functional logic verification, develop verification plans, and collaborate with various teams to improve verification processes.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Performs functional logic verification at multiple levels ( block, subsystem and full chip )
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs
Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests
Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage
Maintains and improves existing functional verification infrastructure and methodology
Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products
Qualification
Required
Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 3-5+ years of technical experience
Validation/Verification. Related technical experience should be in/with: Pre Silicon
OVM/UVM, System Verilog, constrained random verification methodologies
Preferred
Design Verification with developing, maintaining, and executing complex IPs and/or SOCs
The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies
Scripting experience with TCL/PERL/Python etc
Formal verification experience
Experience in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
Company data provided by crunchbase