Silicon Design Package Engineer - Tech M jobs in United States
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Saransh Inc ยท 1 month ago

Silicon Design Package Engineer - Tech M

positionSanta Clara, CA
timeContract
remoteOnsite
seniorityMid Level

Saransh Inc is seeking a Silicon Design Package Engineer who specializes in semiconductor packaging design. This role requires strong proficiency in EDA tools and knowledge of advanced packaging technologies.

EmploymentInformation TechnologyStaffing Agency
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H1B Sponsor Likelynote

Qualification

EDA tools proficiencyMulti-layer package designSubstrate manufacturing rulesSIPI rulesFlip-chip package designMentor/Siemens toolsCadence tools

Required

Strong EDA tool proficiency
Knowledge of advanced packaging technologies
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA)
Multi-layer package design experience
Understanding of substrate manufacturing Design Rules and Assembly Rules
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules
Flip-chip package design concepts

Company

Saransh Inc

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We provide recruitment, consulting and IT services for our clients, which focus on maximizing their revenue generation, enhancing business productivity and improving cost management.
dateFounded in 2008
location
Plainsboro, New Jersey, USA
people-size51-200 employees
web-link
https://saranshinc.com

H1B Sponsorship

Saransh Inc has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (35)
2024 (51)
2023 (45)
2022 (30)
2021 (22)
2020 (39)

Funding

Current Stage
Growth Stage

Leadership Team

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Sridhar Chimaladinne
FOUNDER & CEO
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Company data provided by crunchbase