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PER International · 3 days ago

Senior Design Verification Engineer

Santa Clara, CA

Contract

Onsite

Senior Level, Lead/Staff

8+ years exp

PER International is seeking a high-performing SoC verification specialist for their fast-moving Bay Area hardware team. The role involves taking ownership of verification for complex I/O and interconnect subsystems and requires building clean, scalable verification environments while solving tough debug problems.

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Hiring Manager

Jaimie Javier

Responsibilities

Own verification for complex, multi-IP subsystems (I/O, interconnect, networking/packet flows depending on project scope)

Define verification strategy, plans, and sign-off criteria aligned to architecture requirements

Build and maintain robust UVM verification environments using SystemVerilog

Create high-quality constrained-random tests, checkers, scoreboards, and coverage models

Drive protocol-level verification and debug, with a strong emphasis on PCIe behavior and corner cases

Debug issues across simulation, waveforms, RTL, and (where relevant) firmware/software interactions

Collaborate with distributed teams (including India and potentially East Asia), supporting reviews and execution

Qualification

Design VerificationSystemVerilogUVMPCIe VerificationConstrained-Random VerificationSVADV ToolchainsCommunication SkillsTeam Collaboration

Required

8+ years hands-on Design Verification / Verification experience in semiconductor, networking, compute, or accelerator-class hardware

Strong SystemVerilog and UVM expertise (including building/owning UVM environments)

Proven PCIe verification experience (Gen4/5/6 exposure is a plus, but PCIe depth is required)

Solid background in constrained-random verification and coverage-driven methodologies

Ability to independently drive tasks, communicate clearly, and deliver to sign-off quality

Preferred

SVA (SystemVerilog Assertions) and assertion-based verification

Experience with one or more of: UCIe / die-to-die interfaces / chiplet-based systems, CXL-class fabrics / UALink or similar high-speed interconnects, Ethernet/networking protocols, Packet-processing architectures or networking datapaths

Experience verifying large-scale subsystems with multiple interacting IPs

Track record working with international teams in a lead or mentoring capacity

Familiarity with common DV toolchains (e.g., VCS/Xcelium/Questa, Verdi/DVE, regression automation)