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Marvell Technology · 3 weeks ago

Principal Advanced Packaging Design Engineer

Burlington, VT

Full-time

Onsite

Lead/Staff

8+ years exp

Marvell Technology is a leading semiconductor solutions provider, focused on enabling innovative technology across various sectors including enterprise and AI. The Principal Advanced Packaging Design Engineer will lead small project teams to deliver high-quality packaging solutions, interfacing with suppliers to ensure manufacturability and compliance with performance requirements.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Leading small project teams of design and simulation engineers to deliver innovative high quality packaging solutions

Interfacing with package suppliers to select package technology to ensure manufacturability, and compliance with performance, reliability, and cost requirements

Qualification

Advanced package technologiesCadence 3DIC/ISP/APD/SiPSignal integrityPower integrity2.5D/3D package technologyCadence Sigrity/Clarity/Innovus/VirtuosoAnsysAutoCADSolidWorksInterpersonal skillsCommunication skillsPresentation skillsDocumentation skills

Required

Extensive experience in substrate and/or board design for advanced package technologies with basic understanding of design for manufacturing and reliability as well as electrical performance and the ability to make trade off decisions accordingly

Proven ability to lead complex package architecture development projects involving all relevant internal and external customer stakeholders

Mastery in tools and workflows: Cadence 3DIC/ISP/APD/SiP

Bachelor's degree in electrical engineering or related fields and 15+ years of related professional experience or master's degree and 12+ years of related professional experience or PhD degree with 8+ years of experience

Innovative thinking, fundamental understanding of design rules, breakout, place and route, signal shielding, reference plane, power distribution, pinout considering overall package and system requirements

Experience with current generation HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIE, Ethernet, etc

Good understanding of signal and power integrity at substrates, board, package, and system level

Understanding of advanced 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB, (c) CPO, (d) CPC

Familiarity in tools and workflows: Cadence Sigrity/Clarity/Innovus/Virtuoso, Ansys, AutoCAD, SolidWorks

Experience contributing to tool, process, and flow development, library maintenance

Experience interacting with chip design and electrical simulation teams to optimize the design. Familiarity with running and interpreting signal and power simulations is a plus

Ability to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe

Strong communication, presentation and documentation skills