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Advanced Microdevices Pvt. Ltd. (India) · 3 weeks ago

Principal Interconnect Micro-architect and RTL Design Engineer

Santa Clara, CA

Full-time

Hybrid

Lead/Staff

Advanced Micro Devices, Inc is focused on building innovative products that enhance next-generation computing experiences. They are seeking a Principal Interconnect Micro-architect and RTL Design Engineer to lead the development of scalable, modular network on chip IPs for AMD Data Center silicon SoCs, ensuring optimal power, performance, and area.

BiopharmaBiotechnologyIndustrialManufacturing

Responsibilities

Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, performance, and area

Explore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced Data Center AI acclerator SOCs

Develop technical relationship with broader AMD design community and peers

Stay informed on latest trends on innovations on switch fabric hardware architecture and implementation

Close architecture, and micro-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution

Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirements

Knowledge sharing and other contributions to AMD Data Fabric architecture and design

Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs

Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Qualification

Microarchitecture designRTL designPower optimizationVerilogSystemVerilogScripting languagesSoC architectureCommunication skillsCollaboration skillsPresentation skills

Required

Proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power

Ability to communicate effectively and work optimally with different teams across AMD

Passion for modern, complex microarchitecture, and efficient digital design

Demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP

Possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time

Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, performance, and area

Explore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced Data Center AI accelerator SOCs

Develop technical relationship with broader AMD design community and peers

Stay informed on latest trends on innovations on switch fabric hardware architecture and implementation

Close architecture, and micro-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution

Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirements

Knowledge sharing and other contributions to AMD Data Fabric architecture and design

Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs

Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Bachelors or Masters degree in computer engineering/Electrical Engineering preferred

Preferred

Experience with highly scalable, configurable switch fabrics (coherent and non-coherent)

Experience with modern heterogenous systems including CPU, GPU, and AI accelerators

Experience with SOC and IP creation automation for different microarchitectures

Proven track record of defining and delivering complex IP and SOC microarchitectures

Expert level ability in optimizing and performing tradeoff analysis across multiple domains including PPA, design, microarchitecture, and architecture, verification, and schedule

Expert of RTL design, Verilog and SystemVerilog

Deep knowledge of front-end tools

Experience with synthesis, static timing, DFT

Exposure to physical design and verification methods

Experience with scripting languages such as Perl, Python, Unix shells and Makefiles, and leveraging AI tools to improve productivity

Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-systems, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security

Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads

Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design

Excellent communication, management, and presentation skills

Adept at collaboration among top-thinkers and senior architects and designers with strong interpersonal skills to work across teams in different geographies