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PHIZENIX · 3 weeks ago

Virtual Platform Hardware Modeling Engineer

Sunnyvale, CA

Full-time

Hybrid

Entry, Mid Level

2+ years exp

PHIZENIX is seeking a modeling Engineer to develop high-level models of complex SoC hardware. The role involves designing and developing SystemC TLM models, integrating various models into a virtual platform, and collaborating with other engineers to ensure accurate silicon validation.

Information Technology & Services

Hiring Manager

Pradeep Sain

Responsibilities

Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…

Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration

Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP

Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks

Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption

Qualification

C++Hardware simulationSoC architectureSystemC/TLMPerformance modelingPythonContinuous integrationDebugging toolsVerilogProcessor architecturesCache modeling

Required

B.S. degree in Computer Science or Electrical Engineering or equivalent experience

2+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators

High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation

General familiarity with SoC components: embedded processors such as ARM A/M series, Risc-V, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols. Extensive experience in at least one of these areas

Experience with modern build frameworks and continuous integration systems, such as CMake, Bazel and CI frameworks such as Jenkins, GitLab CI/CD

Experience with debugging and profiling tools, such as GDB or other debuggers

Preferred

Experience with the SystemC/TLM library

Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models

Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa

Familiarity with NoC, MMU, address translations, and cache modeling

Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…

Proficiency in Python to automate design flows, creation of collateral data

Experience with high level C/C++ synthesis (HLS)

Working knowledge of Verilog