Cadence · 1 day ago
DSP or Serdes RTL Sr Principal Digital Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$154K/yr - $286K/yr
10+ years expCadence is a company focused on developing leaders and innovators in technology. They are seeking a highly self-motivated engineer to join their team, responsible for front-end coding, scripting, and developing flows in digital design and functional verification.
AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
Hiring Manager
Mark Apton
Responsibilities
Digital microarchitecture definition and documentation
RTL logic design, debug and functional verification
Strong background in DSP and algorithms is a plus
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus
Understanding of digital architecture trade-offs for power, performance, and area
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow
Exhibit excellent communication skills and be self-motivated and well organized
Experience with FPGA and/or emulation platform is a plus
Firmware development of embedded microcontroller systems is a plus
Qualification
Required
At least 10 plus years of actual work experience in SerDes
Thorough understanding of the end-to-end digital design flow
Digital microarchitecture definition and documentation
RTL logic design, debug and functional verification
Understanding of digital architecture trade-offs for power, performance, and area
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow
Exhibit excellent communication skills
Self-motivated and well organized
Substantial experience with Verilog
Excellent logic and debug skills
Preferred
Strong background in DSP and algorithms
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol
Experience with FPGA and/or emulation platform
Firmware development of embedded microcontroller systems
Engineering expertise in mixed-signal IP development procedures
Ethernet connectivity protocol knowledge
Benefits
Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
A variety of medical, dental and vision plan options
And more
Company
Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
10001+ employees
H1B Sponsorship
Cadence has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (306)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO
Leadership Team
Paul Cunningham
Senior Vice President and General Manager
Tom Beckley
Senior Vice President, Custom IC & PCB Group
Recent News
2026-01-07
2026-01-06
Company data provided by crunchbase