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PER International · 3 weeks ago

Senior Staff RTL Design Engineer

California, United States

Full-time

Hybrid

Senior Level

5+ years exp

PER International is recruiting on behalf of a leading semiconductor design house based in Silicon Valley. They are seeking a highly-skilled Senior Staff RTL Design Engineer for a purely digital design role, responsible for the micro-architecture and implementation of complex logic blocks for next-generation SoCs.

Professional ServicesRecruitingStaffing Agency

Hiring Manager

Maria Mercado

Responsibilities

Define micro-architecture and write high-quality, synthesizable RTL code (Verilog/VHDL) for complex digital logic blocks

Run synthesis using tools like Synopsys or Cadence to analyze and optimize for power, performance, and area (PPA)

Collaborate closely with verification teams to create test plans and debug simulation failures

Work with physical design teams to meet timing closure and manage physical constraints

Participate in design reviews and contribute to a culture of technical excellence

Qualification

RTL designVerilogVHDLSynthesisASIC/SoC designComplex logicPPA analysisPythonC/C++Shell scriptingMaster's DegreeFluency in Mandarin

Required

5 to 15 years of experience in ASIC/SoC digital design

A minimum of 4 years of hands-on RTL design experience in Verilog or VHDL

You must have been actively writing RTL and designing complex logic within the last 2 years

Proven experience (within the last 2 years) designing complex logic for one or more of the following: Video CODEC, CPU/GPU, Signal Processing Chips (e.g., DSPs, ISPs)

At least 2 years of total experience running synthesis and analyzing PPA reports. (This experience does not need to be recent, but you must have hands-on experience with the tools)