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Boeing · 3 weeks ago

ASIC and/or FPGA Design and Verification Engineers (Entry Level, Associate, or Experienced)

USA - Mountain View, CA

Full-time

Onsite

Entry, Mid, Senior Level

$115K/yr - $155K/yr

The Boeing Company has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers to join their Electronic Products team. The role involves developing state-of-the-art digital ICs/SoCs to support critical programs across the enterprise.

AerospaceIndustrial

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs

Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance

Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)

Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed

Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule

Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation

Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards

Drive FPGA-based prototyping and validation depending on program and system requirements and complexity

Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed

Qualification

ASIC designFPGA designSystemVerilogDigital IC designHardware verificationObject Oriented ProgrammingScripting languagesLinux environmentsFunctional Coverage ModelsSelf-checking testbenchesHigh-speed Serdes interfacesRevision Control SystemsRadiation mitigation

Required

Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement

ASIC/FPGA design or verification knowledge

Preferred

Associate, Level 2: 2+ years of related work experience

Experienced, Level 3: 5+ years of related work experience

Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience

Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs

Experience with hardware emulators, especially Palladium

Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

Ability to executable test plans

Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc

Ability to create self-checking and reusable testbenches from scratch

Experience developing Functional Coverage Models and Closing Code Coverage

Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)

Proficient in scripting languages: Make, Perl, Python, etc

Revision Control Systems: svn, cvs, git

Proficient in Linux Environments

Familiarity with space-based design techniques and radiation mitigation

Demonstrated history of 1st pass success with ASIC designs