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Analog Devices · 3 days ago

Senior Digital Design Engineer

Chandler, AZ

Full-time

Onsite

Mid, Senior Level

4+ years exp

Analog Devices is a global semiconductor leader that bridges the physical and digital worlds. They are seeking a Senior Digital Design Engineer to verify and design integrated circuits and support products through the full product life cycle in the Power Solutions Group.

DSPElectronicsLightingSemiconductor

No H1B

U.S. Citizen Only

Responsibilities

Definition of interfaces, state machines, and controlling logic required to implement new products in a wide range of application spaces

RTL digital design and problem solving

Digital synthesis, place-and-route supervision, including STA, LEC, GLS, etc. tasks as needed by the project

Development of directed and constrained random test cases in SystemVerilog

Qualification

Digital IC DesignSystemVerilogFPGA DevelopmentScripting LanguageUVM UnderstandingCustom Digital InterfacesDriveCommunication SkillsDocumentation SkillsProblem SolvingOwnership

Required

Bachelor's Degree

4 years of Digital IC Design experience with BSEE or 2 years with MSEE

Strong written and verbal communication skills

Strong general coding and documentation skills

SystemVerilog fluency in design

Experience with a scripting language (Perl, Python, C, etc.)

Fundamental understanding of UVM

Ability to own and drive assignments to completion with little supervision

Hands-on development, implementation, and validation of FPGA, including synthesis, timing closure, and system integration

Ability to learn and master the full digital verification process

Preferred

Working experience with custom digital interfaces (I2C, SPI, UART, etc.)

Design experience with custom state machines and control logic for use with analog circuits such as linear regulators, DC-DC converters, data converters, and mixed signal processing functions

RTL design for synchronous applications, including multiple clock domains (asynchronous design experience a plus)

Logic synthesis, interfacing with place & route staff, static timing analysis, logic equivalency checking, etc

Design for test, scan insertion, ATPG, functional test vectors, etc

Mixed-signal simulation (Cadence AMS), interfacing with analog functions (Verilog-AMS or real number modeling experience a plus)

System Verilog Assertion for Dynamic and Formal Verification

Verification test plan creation, coverage closure, test case, and regression suite development

Advanced knowledge of complex IC verification techniques (SystemVerilog/UVM)