Western Digital · 3 weeks ago
Technologist - Analog/Mixed-Signal CAD Development Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$171K/yr - $227K/yr
8+ years expWestern Digital is a leader in data storage technology, dedicated to powering global innovation. They are seeking a Technologist to focus on the development of EDA design environments for analog/mixed-signal ASIC design, including tool evaluation, automation, and quality improvement methodologies.
Big DataComputerHardwareManufacturingSoftware
Responsibilities
Continued development of concepts and methods for the EDA design environments with focus on analog / mixed signal ASIC design in advanced nodes
Tool evaluation, testing, validation and customer support
Automation and Utilities development in Cadence SKILL/SKILL++
Development of Calibre/Pegasys Physical Verification decks for CMOS PLANAR technologies including DRC, LVS, PERC, FILL LPE and shape generation
Create appropriate test circuits and structures, to validate verification rules and to troubleshoot errors
Development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation
Collaboration with IT team to fulfil advanced nodes specific requests (Linux, Exceed-on-Demand, Grid, VMWare-ESX, Storage-system, etc.)
Ensuring the operation and support within the CAD / IT-team for all ASIC designers worldwide
Managing the quality and ISO26262 requirements for the EDA tools, both for in-house developments and vendor products
Effectively manage PDK libraries, collaterals and drive migration of design environments for incremental releases
Qualification
Required
University degree (BS/MS/PhD) in electrical or computer engineering or a comparable subject
Communicative, problem-solving mindset, responsible, takes initiative, flexible and target oriented. Comfortable in working in a fast paced, dynamic environment with changing priorities
Minimum 8+ years of development experience of Mixed Signal CAD design Flows from Front to Back
Deep experience with industry standard EDA tools such as Virtuoso, Quantus, Pegasys, Spectre, Calibre, StarRC, PrimeSim, Totem, Voltus
Thorough understanding of Custom Analog development flows and methodologies. Experience with physical verification methodologies for DRC, LVS and parasitic extraction, Calibre, starRC, ICV etc
Cadence Skill, Calibre SVRF/TVF, Python, Shell
Deep knowledge of PDK and collateral, installation, management and integration into CAD tools
Proficient knowledge of revision control software (Git, Perforce, Subversion, Synchronicity, etc)
Working knowledge of analog and mixed-signal design process and concepts such as matching, symmetry, layout effect, monte-carlo, electro-magnetic analysis
Preferred
Bonus – past experience with AI/ML based projects with layout and design acceleration
Benefits
Paid vacation time
Paid sick leave
Medical/dental/vision insurance
Life, accident and disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
Tuition reimbursement
Transit
The Applause Program
Employee stock purchase plan
Western Digital Savings 401(k) Plan
Company
Western Digital
Western Digital helps customers capture, preserve, access, and transform an ever-increasing diversity of data.
10001+ employees
H1B Sponsorship
Western Digital has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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Trends of Total Sponsorships
2025 (234)
2024 (537)
2023 (448)
2022 (580)
2021 (525)
2020 (332)
Funding
Current Stage
Public CompanyTotal Funding
$901.37M2023-10-31Post Ipo Debt· $1.37M
2023-01-31Post Ipo Equity· $900M
2015-09-30Post Ipo Equity
Leadership Team
Sesh Tirumala
SVP, CIO
A
Alvin B. Phillips
Founder
Recent News
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