Design Verification Engineer jobs in United States
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Meta · 21 hours ago

Design Verification Engineer

positionSunnyvale, CA
timeFull-time
remoteOnsite
senioritySenior Level
money$146K/yr - $209K/yr
date6+ years exp

Meta is a technology company focused on connecting people and building immersive experiences through augmented and virtual reality. They are seeking a Design Verification Engineer to define and implement verification plans, develop functional tests, and collaborate with cross-functional teams to ensure high design quality.

Computer Software
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Comp. & Benefits

Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Qualification

SystemVerilog/UVMC/C++ verificationIP/SoC verificationEDA toolsPython scriptingDesign Verification infrastructureUniversal Verification MethodologyRevision control systemsAudio/image/Video processing

Required

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred

Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation
Prior working knowledge of Audio/image/Video processing compute intensive cores

Benefits

Bonus
Equity
Benefits

Company

Meta

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Meta's mission is to build the future of human connection and the technology that makes it possible.
dateFounded in 2004
location
Menlo Park, CA, US
people-size10001+ employees
web-link
https://www.metacareers.com/

Funding

Current Stage
Late Stage

Leadership Team

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Kathryn Glickman
Director, CEO Communications
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Christine Lu
CTO Business Engineering NA
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