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Meta · 22 hours ago

ASIC Engineer, Design Verification

Sunnyvale, CA

Full-time

Onsite

Entry, Mid Level

$114K/yr - $172K/yr

2+ years exp

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. The role involves verification closure of design modules for data center applications, including developing test plans and collaborating with cross-functional teams to ensure high design quality.

Computer Software

Comp. & Benefits

Responsibilities

Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification

Develop functional tests based on verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Qualification

SystemVerilog/UVMSoC verificationEDA toolsC/C++ verificationPython scriptingDesign verification infrastructureDebuggingFirst-pass successCollaboration

Required

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta

2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification

2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred

Experience with revision control systems like Mercurial(Hg), Git or SVN

Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycles

Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch

Experience with IP or integration verification of high-speed interfaces like Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR), Ethernet

Experience with verification of Advanced RISC Machines/Reduced Instruction Set Computing Five (ARM/RISC-V) based sub-systems or System-on-Chip (SoCs)