SoC Silicon Top-Level Floorplan Engineer jobs in United States
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Google · 4 weeks ago

SoC Silicon Top-Level Floorplan Engineer

Google is a leader in technology and innovation, and they are seeking a SoC Silicon Top-Level Floorplan Engineer to drive cutting-edge TPU technology for AI/ML applications. The role involves creating the initial physical layout of a chip, defining block sizing and placement, and collaborating with various teams to ensure performance and efficiency in chip design.

AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Own the planning, creation, and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume
Resolve structural or physical issues related to the integration of complex ASICs and SoCs and collaborate with teams across Google to develop ideas for high impact Silicon and Hardware projects
Manage all cross-functional interactions related to top-level floorplanning of chip projects
Develop and improve floorplan implementation methodologies. Support and execute implementation flows using both industry-standard and specialized internal tools
Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area and cost goals

Qualification

Physical design experience3D IC design experienceScripting languagesEDA tools expertiseSoC design methodologiesCross-functional collaborationBachelor's degreeMaster's degreePhDTechnologies

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
10 years of experience in physical design (e.g., with a focus on floorplanning, integration, or top-level chip assembly)
Experience in physical design working on advanced nodes
Experience collaborating with cross-functional teams (e.g., architecture, RTL design, synthesis, verification)
3D IC design experience (e.g., multi-die partitioning, TSV planning, advanced chiplet and packaging technologies, optimizing PPA, and physical verification in a System-in-Package context)

Preferred

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Experience in scripting languages (e.g., Python, Tcl or Perl) and industry standard top-level tools including Innovus, FusionCompiler
Experience working on various technologies (e.g., embedded processors, DDR, SerDes, HBM, networking-on-chip fabrics, etc.)
Experience using specialized EDA tools to resolve DRC/LVS/EMIR issues for leading edge nodes
Experience with SoC design methodologies for full chip power grid, global clocking, data path implementation, 3PIP integration, and bump planning

Benefits

Bonus
Equity
Benefits

Company

Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.

H1B Sponsorship

Google has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)

Funding

Current Stage
Public Company
Total Funding
$26.1M
Key Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M

Leadership Team

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Sundar Pichai
CEO
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Thomas Kurian
CEO - Google Cloud
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Company data provided by crunchbase