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Celero Communications · 3 weeks ago

Principal Analog Design Engineer – High-Speed Interconnects

Irvine, CA

Full-time

Hybrid

Senior Level, Lead/Staff

5+ years exp

Celero Communications is a fast-growing startup focused on high-speed mixed-signal circuit designs. They are seeking a Principal Analog Design Engineer to lead the development of high-speed interconnect technology for next-generation AI systems, responsible for designing high-performance analog circuitry and leading cross-functional teams.

Semiconductors

H1B Sponsor Likely

Hiring Manager

Mita Crawford

Responsibilities

Design high-speed analog circuits such as broadband amplifiers, drivers (DRV), and transimpedance amplifiers (TIAs)

Develop critical analog blocks including TIA, VGA, CTLE, Pre-DRV, DRV, etc

Innovate and implement new techniques for next-generation optical transceivers

Perform custom passive component design from concept through silicon implementation

Supervise analog layout efforts using advanced process nodes (e.g., FinFET)

Create system-level verification plans and detailed circuit design specifications

Lead silicon bring-up, debugging, and validation efforts

Effectively communicate and document designs within cross-functional teams

Qualification

High-speed analog designAnalog design toolsElectromagnetic simulation toolsSystem-level validationAnalog layout designCommunication skillsDocumentation skills

Required

Master's degree and/or Ph.D. in Electrical Engineering or related fields

5+ years of experience in high-speed analog design

Strong analog design fundamentals with experience in broadband amplifiers, VGA, CTLE, TIA, DRV (>50GHz Bandwidth)

Proficient with analog design and verification tools (Virtuoso, Spectre, ADE, post-layout extraction tools)

Experienced with electromagnetic simulation tools (EMX, Momentum, HFSS, or equivalent)

Strong understanding of electromagnetism, lumped models, and high-frequency design principles

Experience with system-level pre-tape-out analog validation

Understanding of analog layout design in FinFET processes and its impact on performance

Excellent communication and documentation skills

Preferred

Master's degree and/or Ph.D. (preferred) in Electrical Engineering or related fields

Experience in lab chip bring-up and debugging is a plus

Company

Celero Communications

Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure.

Founded in 2024

Irvine, CA, US

51-200 employees

https://celero.inc

H1B Sponsorship

Celero Communications has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

Distribution of Different Job Fields Receiving Sponsorship

Represents job field similar to this job

Trends of Total Sponsorships

2025 (3)