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AMD · 3 days ago

Physical Design PPA

Fort Collins, CO

Full-time

Onsite

Mid, Senior Level

$139K/yr - $209K/yr

AMD is a company focused on building innovative products that enhance computing experiences across various domains. In this role, you will work within the physical design central methodology team to define methodologies for high-performance computing chips, collaborating across divisions to optimize physical design processes.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Drive PVT corners/ frequency targets while considering various product performance modes and guard bands

Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt

RTL (architecture) and PD co-development to identify bottlenecks

Drive budgeting, measurement, analysis and tracking of power-consumption

Establish global methodologies and best-known physical implementation recipes for optimal performance/watt across library/flow/Synthesis/P&R environment

Drive best practices for global/local clock distribution methodologies including skew/power/jitter trade-off’s

Create guidelines on clocking/timing/power sign-off methodologies

Qualification

Physical design methodologyPower analysis toolsHigh-performance clockingSub-micron design experienceCPU/GPU architectureSTA methodologiesScripting languagesAttention to detailCollaborationProblem-solving

Required

Drive PVT corners/ frequency targets while considering various product performance modes and guard bands

Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt

RTL (architecture) and PD co-development to identify bottlenecks

Drive budgeting, measurement, analysis and tracking of power-consumption

Establish global methodologies and best-known physical implementation recipes for optimal performance/watt across library/flow/Synthesis/P&R environment

Drive best practices for global/local clock distribution methodologies including skew/power/jitter trade-off's

Create guidelines on clocking/timing/power sign-off methodologies

MS/PhD degree in Electrical Engineering is preferred

Mastery of logic, circuit design, and CAD tools for high-performance design is expected