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Meta · 1 day ago

ASIC Engineer, SoC Verification

Sunnyvale, CA

Full-time

Onsite

Senior Level, Lead/Staff

$178K/yr - $250K/yr

8+ years exp

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. The role involves building IP and System On Chip (SoC) for data center applications, focusing on verification closure of design modules through various methodologies, and collaborating with cross-functional teams to ensure high design quality.

Computer Software

Comp. & Benefits

Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

Develop functional tests based on verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Qualification

SystemVerilogUVM methodologyC/C++ verificationDesign VerificationEDA toolsPython scriptingChip DebugBootCPU SubsystemsPCIeNICMemory Subsystems

Required

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Track record of 'first-pass success' in ASIC development cycles

8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification

8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred

2+ years of experience in SoC Level for CPU, GPU, or AI accelerator architectures

Hands on experience with leading the full verification cycle of a SoC or a complex sub-systems to verification to closure on multiple projects, preferably on AI Accelerators

Experience in supporting and partnering with Emulation, Firmware and/or Post-Silicon Validation teams

Expertise in at least 2 of the following – Chip Debug, Boot, CPU Subsystems, Chip level Clock/Reset, PCIe, NIC, Memory Subsystems

Familiarity with developing System level use-cases and End-to-end tests at SoC level

Familiarity with debugging large design on Emulation platforms

Prior experience in supporting Silicon bring-up, translating system level use-cases into specific test scenarios at SoC level